Yamaha DX7II-FD/D Uživatelský manuál

1 FPGA - DX7 EDA385 - Project Report Andreas Irestål ( [email protected] ) Rajanarayana Priyanka, Marigi ( [email protected] ) Shadi Abd

10 Figure 4: A Project in the Ableton Live music software with a VST plugin inserted.

11 3 FPGA Hardware The architecture of the FPGA hardware is shown in figure 5. This architecture is the same as the one initially proposed with the

12 difference between those two states is that the write signal for globals ram is disabled when calculating operators. Figure 5: O

13 3.2 OPS This hardware block generates the musical sound with the frequency and amplitude provided by the EGS, and the algorithm from the so

14 The OPS sample data output has a latency of 114 system clock cycles after the ‘sync’ signal is received from EGS. 3.3 Mixer Mixe

15 The UART controllers above work in such a way that they generate an interrupt on data reception that could be treated differently if the re

16 Figure 7: Sound Generator (OPS) block diagram

17 Figure 8: Phase Accumulator Schematic

18 4 MicroBlaze Software The Microblaze software, explained in section 4.1, interfaces with the MIDI and VST Control inputs by way of an interru

19 The main function can be found in the dx7main.c source file. 4.2 The Interrupt System As mentioned earlier the software takes care of incoming in

2 Abstract The project closely recreates a Yamaha DX7, a FM synthesizer using a Nexys 2 FPGA board, I2S pmod, MIDI keyboard, VST plugin and a MIDI &

20 where usbin_int_handler is the high-level interrupt handler where the actual interrupt handling is done. As interrupts stop the normal execution

21 Following the same principle as MIDI decoding, once a VST message has been decoded a call is made to the corresponding function to set a parameter

22 5 External hardware and software In this section we describe any hardware and software external to the FPGA. These consist of a MIDI & USB co

23 ● As long as the plugin stays instantiated and enabled, the host communicates any automation changes, note events and changes in the plugin contr

24 6 Implementation Problems This section elaborates on the main implementation issues we experienced. Section 6.1 discusses the problem w

25 As mentioned earlier, all exponential representations have caused a lot of problems as well. This has been the case in hardware, since it is extra

26 7 Results In this section we list the features that have been implemented and are working correctly. While section 7.1 deals with

27 The FPGA synthesizer synchronizes its set of parameter values with the VST plugin and subsequently decodes and processes any parameter changes

28 8 In hindsight ... In this section we list things we could have done differently. Most of these were not explored further or tried out due to the

29 9 Possible extensions In this section we list possible extensions that could be made to the project given enough time. SysEx Patch Bank Trans

3 Table of Contents FPGA - DX7 ...

30 10 Lessons Learned Shadi Abdu-Rahman: Working on this project included many ‘first times’ for me: Developing with Apple’s Xcode, coding a

31 11 Contributions Shadi Abdu-Rahman: ● Project Report: Layout, writing or contributing to sections 2.3, 2.4, 3.6 , 4.1 - 4.6, 5.1 - 5.2, 6.1 -

32 12 References 1. http://www.abdn.ac.uk/~mth192/dx7/manuals/dx7-man.pdf 2. http://www.abdn.ac.uk/~mth192/dx7/manuals/dx7-9_service_manual_1.pdf

33 Appendix A: Tools used ● Xilinx Platform Studio 12.2 ● ISE Project Navigator ● Digilent Adept ● Apple Xcode 4.2 ● Notepad++ 5.9.3 ● PuTTY 0

34 Appendix B: Installation Entire system setup: 1. Connect an I2S pmod and a MIDI & USB connector board with pmod connector to Pm

35 Appendix C: User Manual Using Digilent Adept download the bit file to FPGA board. And now just start playing your heart on MIDI keyboard! The

36 Appendix D: FSL-DX7 Protocol The messages are 32 bits wide. The fields definition and width changes depending on the destination component except

37 31-28 (4) 27-25 (3) 24-25 (2) 22-8 (15) 7-0 (8) Don’t care “111” “11” Don’t care Pan Messages to EGS can be global (Pitch Envelope Genera

38 “010” PEG level 3 12 “011” PEG level 4 12 “100” LFO delay 20 “101” Pitch Modulation Sensitivity 12 “111” LFO parameters (Speed + Sync + Wave + Key

39 “110” Op parameters (Base amplitude + Sync on + Operator on) 14 31-28 (4) 27-25 (3) 24 (1) 23-21 (3) 20-5 (12) 4 (1) 0 (1) Channel Operator “0” “

4 10 Lessons Learned ... 30 11 Contributions ..

40 Appendix E: XPS Block Diagram A block diagram of entire system as generated by EDK XPS is shown in figure 9. Figure 9: XPS block diagram

5 1 Introduction In this project, a FM synthesizer is created using the Nexys2 FPGA board. This type of sound synthesis was popular

6 2 Background In this section background information on the technologies used is provided: In section 2.1 the basics of FM synthes

7 FM generates frequency components in the output waveform that are not necessarily harmonically related to the carrier or modulator frequency

8 defines the instantaneous values of these parameters applied. When applied to a carrier however, it defines the loudness. The envelope closely foll

9 The output of sound generating engine is fed to the mixer which applies the global volume and panning parameters. Then it is applie